# X86.MXCSRBits > The 32-bit MXCSR register contains control and status information for SSE and AVX SIMD floating-point operations. ## Definition * **Type:** Enum * **Namespace:** [Unity.Burst.Intrinsics](/engine/6000.7/script-reference/unity/burst/intrinsics.md) * **Assembly:** UnityEngine.BurstModule ```csharp [Flags] public enum X86.MXCSRBits ``` ## Fields | Value | Description | | ---------------------------------------------------------------------------------------------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | | [DenormalFlag](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/denormalflag.md) | Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them. | | [DenormalOperationMask](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/denormaloperationmask.md) | Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked. | | [DenormalsAreZeroes](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/denormalsarezeroes.md) | Bit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which controls the processor’s response to a SIMD floating-point denormal operand condition. | | [DivideByZeroFlag](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/dividebyzeroflag.md) | Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them. | | [DivideByZeroMask](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/dividebyzeromask.md) | Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked. | | [ExceptionMask](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/exceptionmask.md) | Combine all bits for exception masking into one mask for convenience. | | [FlagMask](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/flagmask.md) | Combines all bits for flags into one mask for convenience. | | [FlushToZero](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/flushtozero.md) | Bit 15 (FTZ) of the MXCSR register enables the flush-to-zero mode, which controls the masked response to a SIMD floating-point underflow condition. | | [InvalidOperationFlag](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/invalidoperationflag.md) | Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them. | | [InvalidOperationMask](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/invalidoperationmask.md) | Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked. | | [OverflowFlag](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/overflowflag.md) | Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them. | | [OverflowMask](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/overflowmask.md) | Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked. | | [PrecisionFlag](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/precisionflag.md) | Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them. | | [PrecisionMask](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/precisionmask.md) | Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked. | | [RoundDown](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/rounddown.md) | Rounded result is closest to but no greater than the infinitely precise result. | | [RoundingControlMask](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/roundingcontrolmask.md) | Mask for rounding control bits. | | [RoundToNearest](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/roundtonearest.md) | Rounded result is the closest to the infinitely precise result. If two values are equally close, the result is the even value (that is, the one with the least-significant bit of zero). Default. | | [RoundTowardZero](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/roundtowardzero.md) | Rounded result is closest to but no greater in absolute value than the infinitely precise result. | | [RoundUp](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/roundup.md) | Rounded result is closest to but no less than the infinitely precise result. | | [UnderflowFlag](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/underflowflag.md) | Bits 0 through 5 of the MXCSR register indicate whether a SIMD floating-point exception has been detected. They are "sticky" flags. That is, after a flag is set, it remains set until explicitly cleared. To clear these flags, use the LDMXCSR or the FXRSTOR instruction to write zeroes to them. | | [UnderflowMask](/engine/6000.7/script-reference/unity/burst/intrinsics/x86/mxcsrbits/underflowmask.md) | Bits 7 through 12 provide individual mask bits for the SIMD floating-point exceptions. An exception type is masked if the corresponding mask bit is set, and it is unmasked if the bit is clear. These mask bits are set upon a power-up or reset. This causes all SIMD floating-point exceptions to be initially masked. |