Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see UHADD.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. Equivalent instruction: URHADD Vd.2S,Vn.2S,Vm.2S

public static v64 vrhadd_u32(v64 a0, v64 a1)

v64

v64